1. Field of the Invention
The present invention relates generally to a semiconductor integrated circuit, and, in particular, with emphasis on a semiconductor integrated circuit of the type with combinational and sequential circuits being implemented therein so that the fault coverage of said semiconductor integrated circuit can be improved.
2. Description of the Related Art
The conventional practice of testing a semiconductor integrated circuit of the type described above is to read out data memorized in the sequential circuit by means of the Scan Path circuit system with the intention of improving fault coverage.
FIG. 1a shows a block diagram of a conventional semiconductor integrated circuit. FIG. 1b is a partial circuit diagram of such a semiconductor integrated circuit showing the flip-flop circuit portion constituting the Scan Path circuit.
The construction of the semiconductor integrated circuit referred to above usually incorporates a first combinational circuit 11a which serves to combine data DIN and DT in a prescribed manner, and a sequential circuit 12b consisting of a plurality of flip-flop circuits (latch circuits) to perform sequential processing of the data from combinational circuit 11a when the scan mode control signal SMC is in the inactive mode and a second combinational circuit 11b which serves to yield data DOUT to be delivered externally and data DT to be delivered to combinational circuit 11a as the outputs of the prescribed processing of sequential circuit 12b.
The Scan Path circuit is provided as a part of the sequential circuit 12b described above to serve as a shift register when scan mode control signal SMC is at the active mode. This can be achieved by a plurality of flip-flops 111 and 112a connected to multiplexer 113 as shown in FIG. 1b.
The operation of the semiconductor integrated circuit can be tested by using sequential circuit 12b as the Scan Path circuit. This can be achieved by keeping the scan mode control signal SMC is at the active mode. Thus, improvements in fault coverage can be expected.
Next, a detailed explanation of the operation of sequential circuit 12b is given below. A pair of inputs to multiplexer 113 consists of the serial Scan Path data SIN and of input data IN as is usually the case and available as the output of combinational circuit 11a. Either one of the inputs is supplied to flip-flop 111, as the output of the multiplexer depending on whether the scan mode control signal SMC is at the active or inactive levels.
Among the typical test items of a semiconductor integrated circuit are the one to confirm the output data DOUT of combinational circuit 11b when Scan Path data SIN is set on sequential circuit 12b keeping scan mode control signal SMC is at the active mode. Another typical test item is the confirmation of the output contents of sequential circuit 12b when output data IN of combinational circuit 11a is supplied to the sequential circuit 12b as the input, keeping scan mode control signal SMC is at the inactive mode.
Since a semiconductor integrated circuit can thus be tested as a combinational circuit by using sequential circuit 12b as a shift register, the effect of improving fault coverage has been established.
FIG. 1b shows the construction of each flip-flop 111 (112a) consisting of a first transfer gate T11 (T13) designed to transfer and control the data supplied to the input terminal by turning on and off clock signal CK and the inverted signal thereof, a first inverter IV11 (IV13) designed to invert the level of the output data derived from said first transfer gate T11 (T13) and transfer it to the output terminal, a second inverter IV12 (IV14) designed to invert the level of the data from the first inverter IV11 (IV13) and the second transfer gate T12 (T14) designed to transfer and control the data to a input terminal by turning on and off clock signal CK and the inverted signal thereof in reverse polarity to first transfer gate T11 (T13).
Moreover, the on and off operations of transfer gates T11 and T12 of flip-flop 111 are opposite in polarity to the transfer gates T13 and T14 of flip-flop 112a, respectively, and, therefore, the pair of flip-flops 111 and 112a functions as a D-type flip-flop (data latch circuit).
Since conventional semiconductor integrated circuits are so constructed that sequential circuit 12b is recombined to form a Scan Path circuit when the test mode operation is desired with the intention of improving fault coverage, a large number of input and output terminals are needed to comply with the dual purpose of switching between ordinary and Scan Path circuit operations as well as to apply and extract data in and out of the Scan Path circuit itself. Further, an increase in overhead caused by the use of multiplexer 113 for the circuit recombination is unavoidable.